1. Field of the Invention
The present invention relates to a technology of calculate a delay in designing a semiconductor integrated circuit by estimating a change in a power supply voltage which is estimated to be actually applied to a logic cell or a module based on a distance to a power supply area bump closest to the logic cell or the module and a power supply voltage applied to the power supply area bump for each logic cell or module.
2. Description of the Related Art
Generally, a voltage applied to each logic cell in a semiconductor integrated circuit is lower than a voltage applied to a power supply source, depending on the position at which the logic cell is arranged, the distance of the logic cell from the power supply source or the like. This is caused by voltage change which derives from a wiring parasitic element such as a resistance or a capacitance. The magnitude of the voltage to be applied to each logic cell is one of the important factors which influence the delay of the cell. Therefore, it is important to design the semiconductor integrated circuit not by uniformly applying the voltage of the power supply source to all logic cells but by reflecting the influence of the voltage change of each logic cell.
If the semiconductor integrated circuit is designed without consideration to the influence of voltage change, the error between a delay which is obtained by calculation in a design phase and a measured delay in an actual circuit becomes greater, which causes disadvantages such as the need to redesign the semiconductor integrated circuit. If a semiconductor integrated circuit is to be designed under a design rule of less than 0.5 μm, called “deep submicron”, in particular, it is necessary to fully consider the influence of the voltage change of each logic cell.
Two methods are conventionally known for calculating a delay which reflects the influence of the voltage change of each logic cell as follows. The first method is to calculate a delay by extracting a parasitic element of a power supply wiring which connects a power supply terminal to a logic circuit using layout data and process parameters and by multiplying delay time by a power supply voltage or current coefficient which is calculated based on the extracted parasitic element. The second method is to obtain a delay by applying a maximum or minimum voltage change for an entire chip.
The first method, however, has the following disadvantages. It takes a lot of time to perform calculation, design TAT (Turn Around Time) considerably increases, and it is, therefore, impractical to apply the first method to actual circuit design. The second method has the following disadvantages. If the maximum voltage change is used, the semiconductor integrated circuit is designed under excessive conditions, making it difficult to converge design steps. If the minimum voltage change is used, a margin becomes insufficient, with the result that some circuits malfunction. If so, it takes a long time to analyze the malfunction and yield deteriorates. Therefore, whichever is selected, the maximum or the minimum, design TAT increases.